The term "three-state" as used to describe a digital circuit that drives further circuitry refers to a specific operational mode in which the digital circuit is electronically disconnected from the further circuitry without being physically disconnected from it. More precisely, the digital circuit has an output terminal from which information is supplied to an input point of the further circuitry. While continuing to accept and process input data, the digital circuit can be switched from (a) a condition in which the output terminal exhibits low impedance to the further circuitry as the digital circuit switches between a pair of binary logic states to (b) a condition in which the output terminal exhibits very high impedance to the further circuitry. The latter condition is the third state. Due to the high output impedance, the input point of the further circuitry is effectively disconnected from the output terminal.
Three-state is highly advantageous when the further circuitry is driven by a number of digital circuits, only one of which provides information intended to drive the further circuitry at any given time. By placing the other circuits in the three-state mode, they do not load the further circuitry. This allows it to operate more efficiently. Use of three-state also avoids undesirable interactions among the digital circuits by way of the further circuitry.
A better understanding of three-state is facilitated with the assistance of FIG. 1 which illustrates how it is typically used when transistor-transistor logic (TTL). FIG. 1 shows a prior art system containing M three-state logic circuits 10.sub.1 -10.sub.M, of which at least circuit 10.sub.1 is a TTL gate. Circuits 10.sub.1 -10.sub.M provide a one-bit data bus 12 with digital information in response to digital input singals V.sub.I1 -V.sub.IM and output enabling signals V.sub.OE1 -V.sub.OEM. Data bus 12 is terminated by resistors R.sub.TC and R.sub.TE to respective sources of high and low supply voltages V.sub.CC and V.sub.EE.
The V.sub.OE signals for all but one of circuits 10.sub.1 -10.sub.M are normally at output disabling values that place those M-1 circuits in the three-state mode to electrically disconnect their output terminals from bus 12. The V.sub.OE signal for the remaining one of circuits 10.sub.1 -10.sub.M is at an output enabling value. This enables bus 12 to accept its output signal.
Turning specifically to circuit 10.sub.1, it consists of (a) a TTL input stage 14, (b) a TTL output stage 16 formed with NPN transistors QA, QB, QC, and QD and resistors RA, RB, RC, and RD, and (c) a three-state switching stage 18 formed with a control circuit 20 and NPN transistor QE. Gate 10.sub.1 provides its output signal at an output terminal T.sub.O connected to bus 12. When signal V.sub.OE1 is at the output enabling value, control 20 maintans transistor QE in the off condition to prevent it from affecting output stage 16. Depending on the value of signal V.sub.I1, one of output transistors QC and QD is on while the other is off. This defines two logic states. In both cases, current flows through terminal T.sub.O, so that it exhibits low output impedance.
Control 20 turns transistor QE on when signal V.sub.OE1 is switched to the output disabling value. This causes transistors QA and QB to turn off regardless of their prior conductive conditions which, in turn, similarly causes both of output transistors QC and QD to turn off. Circuit 10.sub.1 goes into the three-state mode. Substantially no current flows through terminal T.sub.O. It now presents a very high output impedance. The presence of two serially connected output transistors (i.e., devices QC and QD) makes TTL very conducive to three-state.
The situation is quite different with ECL. For example, consider FIG. 2a which illustrates how a conventional ECL output stage 22 interfaces with a one-bit data bus 24. Supply voltages V.sub.CC and V.sub.EE which provide power to output stage 22 are typically 0 volt and around -5 volts in ECL.
Stage 22 centers around main NPN transistors Q1.sub.A and Q1.sub.B whose bases respectively receive base input signals V.sub.A and V.sub.B. The emitters of transistors Q1.sub.A and Q1.sub.B are connected together at node N1 in a differential configuration. Their collectors are respectively coupled through small equal-size load resistors R1.sub.A and R1.sub.B to the V.sub.CC supply. A main current source 26 connected between node N1 and the V.sub.EE supply provides a main supply current I.sub.M for transistors Q1.sub.A and Q1.sub.B. An intermediate voltage signal V.sub.ITM representative of the state of stage 22 is taken from a node N2 at the Q1.sub.A collector.
Intermediate signal V.sub.ITM is supplied to the base of an NPN output transistor Q2 whose collector is tied to the V.sub.CC supply. Transistor Q2 is always on during circuit operation. Stage 22 provides its output signal to bus 24 by way of terminal T.sub.O connected to the Q2 emitter. The signal voltage on bus 24 is thus about 1V.sub.BE less than V.sub.ITM. V.sub.BE is the standard voltage of 0.7-0.8 volt that exists across the base-emitter junction of a bipolar transistor when it just reaches full conduction in the forward direction. Bus 24 is terminated by a resistor R.sub.T to a source of a termination voltage V.sub.TT which is usually about 2 volts below V.sub.CC.
Stage 22 is at a high binary state (or logical "1") when transistor Q1.sub.A is off and transistor Q1.sub.B is on. This usually arises when the voltage difference V.sub.B --V.sub.A is about 100 millivolts. None of supply current I.sub.M flows through resistor R1.sub.A. The only current flowing through resistor R1.sub.A is the small current needed to drive the Q2 base. As a result, voltage V.sub.ITM is at a high level near V.sub.CC. Because transistor Q2 is on, current flows through terminal T.sub.O causing it to exhibit a low impedance to bus 24.
Stage 22 goes into a low binary state (or logical "0") when V.sub.B --V.sub.A is reversed so as to turn transistor Q1.sub.A on and turn transistor Q1.sub.B off. All of current I.sub.M flows through resistor R1.sub.A. Voltage V.sub.ITM drops to a low level approxaimtely equal to V.sub.CC -I.sub.M R.sub.1, where R.sub.1 is the resistance of resistor R1.sub.A or R1.sub.B. The voltage swing I.sub.M R.sub.1 is typically in the neighborhood of 1V.sub.BE. Terminal T.sub.O again exhibits a low impedance to bus 24. Stage 22 thus switches between two binary logic states, both at low output impedance.
Applying three-state to ECL is a tough problem, largely because there is only one output transistor rather than two as in TTL. Gustafson et al, "ECL Enhances Proven Parallel Architecture," Northcon/85, 22-24 Oct. 1985, pp. 1-13, discusses some of the difficulties that arise in trying to solve the problem. As a solution, Gustafson et al describe a system in which a "wired-OR" arrangement is combined with bus drivers that provide high output impedance when they are in the low logic state. This system is relatively complex and does not appear particularly efficient or fast. Moreover, it does not truly use three-state.
The Signetics 100123 ECL integrated circuit is a bus driver of the type employed in Gustafson et al. With reference to FIG. 2a, voltage swing I.sub.M R.sub.1 is raised to double its normal value in output stage 22 of the Signetics 100123. This enables transister Q2 to turn off when stage 22 is in the low (but not the high) logic state. Terminal T.sub.O presents a high impedance to bus 24 during that time. Even though the Signetics 100123 still operates in only two different states, it does achieve some of the advantages of three-state. However, the increased voltage and the charging/discharging of the Q2 base during normal switching cause the Signetics 100123 to operate significantly slower than an otherwise comparable ECL device.
In explanation of how wired-OR is used in ECL, FIG. 2b illustrates an ECL output stage 28 having a wired-OR capability. Stage 28 is the same as state 22 depicted in FIG. 2a except that an NPN transistor Q1.sub.C is connected between node N1 and the Q1.sub.B collector. A control voltage V.sub.C is supplied to the Q1.sub.C base.
Transistor Q1.sub.C turns on when V.sub.C is raised to a suitable high value. All of current I.sub.M flows through resistor R1.sub.B. V.sub.ITM thereby goes to its high level irrespective of the values of V.sub.A and V.sub.B. Alternatively, the Q1.sub.B collector could be connected to the Q1.sub.A collector. V.sub.ITM would then go unilaterally to its low level. The wired-OR arrangement comes close to three-state in the sense that stage 28 can be placed at either a high logic state or a low logic state regardless of the values of V.sub.A and B.sub.B. However, wired-OR does not provide a true three-state capability in which there are two binary states at low output impedance and one state at high output impedance.
ECL operates much faster than TTL. Accordingly, it would be highly desirable to have an ECL circuit that can be operated in the three-state mode over the normal ECL output voltage range extending from V.sub.CC -2 volts to V.sub.CC.